1. Field of the Invention
The invention relates to a die seal ring, and more particularly, to a die seal ring capable of blocking noise.
2. Description of the Prior Art
Today the functionality and economics of many consumer products are being transformed by “system-on-chip” (SoC) technology. The continuing increase in the transistor densities means that it is now possible to integrate the processor, peripherals and some or all of the system memory on a single chip.
SoC is an idea of integrating all components of a computer or other electronic system into a single integrated circuit chip. It may contain micro processing core, MPEG core, memory, digital/analog circuits, mixed-signal circuits, and often radio-frequency functions—all on one chip. SoC is believed to be more cost effective since it increases the yield of the fabrication and also its packaging is less complicated.
Referring to FIGS. 1, FIG. 1 illustrates a top view of a SoC structure according to the prior art. As shown in FIG. 1, a semiconductor substrate 12, such as a silicon wafer is provided, in which a die region 14, a die seal ring region 16, and a scribe line region 18 are defined on the semiconductor substrate 12. A plurality of I/O pads 26 is disposed on the periphery of the die within the die region 14. The scribe line region 18 is formed on the exterior side of the die region 14 and the die seal ring region 16 and surrounds the entire die seal ring. The die seal ring region 16 is disposed between the die region 14 and the scribe line region 18, such that the die seal ring could be used as a blocking wall for protecting the die region from external stress while the wafer is diced. The scribe line region 18 is specifically divided into two parts, including a first part 20 and a second part 22. The first part 20 of the scribe line region 18 is adjacent to the die seal ring region 16, in which this part 20 would not be diced by dicing tool while the wafer is diced. The second part 22 is positioned on the exterior side of the first part 20 and a plurality of wafer acceptance test pads 24 are placed on the second part 22 for testing purpose. For illustration purpose, only four pads 24 are shown in FIG. 1. The second part 22 is preferably diced by dicing tool while the wafer is diced along the scribe line region 18.
As the I/O pads 26 disposed in the die region 14 from the above SoC design is immediately adjacent to the die seal ring region 16, noise caused by the I/O pads 26 would easily pass around the die seal ring and expand to the peripheral region and affect the operation of the device. Hence, there is a need in this industry to provide a solution that the noise expansion problems can be addressed or eliminated as early as possible during the design phase both on the aspect of the cost and on aspect of the time-to-market of the products.